1. Field of the Invention
This invention relates to a bipolar semiconductor memory which is word organized and includes a plurality of memory cells arranged in a matrix and selective circuits associated therewith in the word or bit direction, respectively, for selecting memory words in response to receipt of address signals, and more particularly to such apparatus in which, primarily in the selective circuit, each line of the memory matrix is connected to a line decoder at an output switch thereof which is embodied as an emitter follower for word selection.
2. Description of the Prior Art
Integrated semiconductor memories are utilized in a multitude of forms in modern data processing systems. For example they may be constructed as write-read memories having selective access, e.g. random access memory (RAM) in which the information content can be changed by way of the program, or as fixed value memories, e.g. read only memory (ROM) wherein the memory content cannot be changed once the same has been stored, but which will always be requested in the same manner again. In the case of fixed value memories constructed upon a semiconductor base, one differentiates more accurately between the common fixed value memories in which the information content is fixed during production at the manufacturing facility, e.g. fabricated read only memory (FROM) and the so-called programmable fixed value memory, e.g. programmable read only memory (PROM), in which the one who utilizes the memory can program the memory information content in the desired manner in accordance with his own requirements in a single process.
Although these memory types differ from one another, for example even in the embodiment of the memory cell, they have a common basic construction, as is well known in the art. For example, a bipolar memory comprises individual memory components wherein a multitude of memory cells is arranged in the form of a matrix. The memory cells are selectable by way of coincidently triggered word and bit lines. In the case of integrated memory component parts with internal control, the entire electronic system required for the operation of the memory cells is also contained upon the component member. In addition to a buffer for the component selection (chip select) a word decoder and at least one bit decoder are respectively provided, with the help of which an individual memory cell, in the case of bit-organized memories, or, in the case of word-organized memories, respectively, several memory cells, can be selected in one line. The "1-out-of-n" selection of the word line or column lines, respectively, by way of the corresponding decoders is effected in response to address signals which are intermediately stored row-by-row or column-by-column, respectively, in the decoders. Furthermore, a reading circuit is connected with the memory matrix, which reading circuit is connected to a data output buffer and which comprises a number of preamplifiers corresponding to the bits per memory word.
In the case of write-read memories, each component will, in addition, comprise a data input buffer and a write circuit connected therewith which is associated column-by-column with the memory matrix. The write circuit includes driver stages for writing information into the component. In the case of fixed value memories, this electronic unit for writing is omitted; only programmable fixed-value memories will obtain so-called charge networks in place of the writing unit, which networks are triggerable by way of address signals. These charge networks enable a user to adjust a certain information state in an electronic manner by way of the address signals of each memory cell. This happens, for example, in such a way that certain metallic line connections are melted, and thus separated, in all memory cells which are to have one of the two possible information states, for example a logical "1" stored therein, which happens with the help of the charge network. This is a one-time process and is not reversible.
Within the framework of this basic prior art construction of bipolar semiconductor memories, a multitude of variations in technical realization, as might be imagined, are well known in the art. The present invention, however, only relates to bipolar semiconductor memories of the above-mentioned different memory forms which use emitter followers as output switches in their selection circuits, e.g. techniques which are based, for example, upon the so-called emitter-coupled logic as a circuit technique (ECL technique). This circuit technique which, as is well known, is very fast, is relatively expensive and time consuming to produce, but is already used in semiconductor memories in which a very short access time is to be obtained. This is primarily true for fast auxiliary memories in central processing units, such as intermediate memories and micro-program memories in which the access time essentially influences the efficiency of a central processing unit of a data processing system. Emitter followers as output switches in selection circuits, however, are also possible in other circuit techniques; the ECL technique is thus only mentioned here as a typical example for a circuit technique wherein emitter followers are applied in multiple.
Emitter followers as output switches of selection circuits are already known for read-write memories having an average integration degree, for example with memory components of 256 bit memory capacity. Together with other circuit measures, the emitter followers permit a short access time in the prior art memory components. The further development of the prior art memory components to obtain a higher degree of integration, for example a memory component with 1024 bit memory capacity, however, is rendered difficult by these switches, unless unproportionally high access times are complied with, measured in relation to the prior art memory components of an average degree of integration.
This apparent paradox can be explained as follows:
Each emitter follower in a line decoder has its emitter respectively connected to one of the bit lines or word lines of the memory matrix, on the one hand, and to the collector of the transistor forming a constant current source, respectively, together with an emitter resistor. In the case of the "1-out-of n" selection in the decoder, one of its outputs, respectively, i.e. one of the emitter followers, will be selected. The respective emitter is then at a high potential ("high" level). All memory cells connected to one word line, however, have switch capacitances which add up and which cause a noticeable capacitive load at a line in the case of a higher degree of integration of the memory component. This means that capacitances must be recharged in the case of each state change of selected emitter followers, the amount of charge increasing with a growing degree of integration. Thereby, greater recharge currents are required, particularly for changes from a high potential to a low potential ("low" level), in order to obtain steep pulse edges at the emitter follower which are required for a short access time to the memory component.
The smaller the degree of integration, the less this effect becomes noticeable. The capacitor charge is small and, simultaneously, the admissible power consumption is not so critical, i.e. in the case of a fixed loss of the memory component, the admissible loss per bit is higher in the case of a low degree of integration. With an increasing degree of integration, the bit capacitances increase and require greater recharging currents. Simultaneously, however, the demands to the boundaries of the loss per bit in the memory component become greater as a whole, so that two mutually opposite demands are given.
Emitter followers and their properties, for example their behavior when subjected to a capacitive load, have been known for quite some time. For example, one may refer to "Proceedings of the IRE 1958", Page 1240 et seq, and to information contained in Speiser "Impulse Circuits", 1963, Page 88 et seq, based on the former article. In addition to explaining the causes for nonsymmetry in the speed of the two pulse edges when switching from a "low" level to a "high" level, or in the opposite direction, respectively, an emitter follower is suggested which utilizes a combination of two transistors of different conductivity types, as a remedy. Both transistors are jointly controlled via a parallel connection of their base inputs. The two emitters are jointly connected at the output of the switch. This circuit construction remains satisfactory in the practice of the present invention. Even if the signal levels required by such a construction are considered, they cannot be applied generally with different circuit techniques since it requires too great a voltage rise. On the other hand, its effectiveness is due to the fact that complementary transistors with approximately equal static and dynamic characteristic curves are used. Such transistors, however, are difficult to realize in integrated circuits with the narrow tolerance requirements made thereon.